1. Field of the Invention
The present invention provides a transmission circuit to be used in a digital communication system, specifically a transmission circuit that utilizes a hardware circuit to expedite data format converting in a rate adaptation layer of the digital communication system.
2. Description of the Prior Art
Digital communication systems have been established as one of the most important infrastructures of modern information society. As a result, improving signal processing capability of various digital circuits within the digital communication system has become a major focus for the contemporary IT industry.
Please refer to FIG. 1, which is a typical digital communication system 10 that illustrates the process flow for digital data transmission. Digital communication system 10 may be a GSM (global system for mobile communications) system that powers the cellular phone. Digital communication system 10 contains various layers of logical structures, making possible a complete range of digital communication functions. These logical structure layers includes a high level protocol 12, physical layer 14, rate adaptation layer 16 and follow-on wireless transmission network 18. The high level protocol 12 contains a cellular phone driver program, AT instruction interpreter, etc.
When a user sends out wireless data via the digital communication system 10, the high level protocol 12 reads data transmission addresses, formats, and relevant protocols, and processes the data according to the appropriate data type, followed by transmission to the physical layer 14. As illustrated in FIG. 1, there are three different types of data: transparent data 20A, fax data 20B and non-transparent data 20C. While transmitting signals, relevant transmission instruction 20D is also transmitted to the physical layer 14, where further processing on various types of data is undertaken to facilitate wireless data transmission to the wireless transmission network 18. However, different types of data are transmitted to the high level protocol 12 and the physical layer 14 at different transmission rates. Prior to transmitting data wirelessly, buffering and format converting of various types of data (with varying transmission speeds) is needed to unify the rate of data transmission to the wireless transmission network 18, and the rate adaptation layer 16 of digital communication system 10 aims to reconcile the different types of data with varying transmission rates, rendering a unified data transmission rate to the wireless transmission network 18. The rate adaptation layer 16 uses various format converting/data buffer models, ranging from 22A and 22B to 22C, to manage the transparent data 20A, fax data 20B and non-transparent data 20C. In the end, instruction 20D is added to various data formats by the format converting processor 24, forming a data flow with a unified transmission rate, and the data flow is transmitted by the wireless transmission network 18. For instance, within a GSM system the format converting/data buffer 22A includes RA0 converting functionRA0 and encoding; the format converting/data buffer 22B includes a T30 converting function and bit reversal; the format converting/data buffer 22C includes RLP+FCS converting; the format converting processor 24 includes a RA1 converting function. Take RA0 converting function for instance, transparent data 20A could transmit data to rate adaptation layer 16 at 300, 1200, 2400, 4800, 9600 and 14.4 k (14400) bits per second. Assume that a sequential data flow from D1, D2 . . . to D8 are transmitted to the rate adaptation layer 16 at the rate of 2400, 4800, 9600 and 14.4 k bits per second, which leads to RA0 converting function to sequentially output bits flow like St, D1, D2, D3, D4, D5, D8, D7, D8 and Sp, where St and Sp stand for special instructions. Assume the data are transmitted at a slow rate of 1200 bits per second to the rate adaptation layer 16, then the RA0 converting function would output bits flow like St, St, D1, D1, D2, D2, D3, D3, D4, D4, D5, D5, D6, D6, D7, D7, D8, D8, Sp, Sp. In other words, assume the data is transmitted to the rate adaptation layer 16 at a slower rate, then the rate adaptation layer 16 would repeat certain data to generate a higher rate of transmission data. Assume the data are transmitted to the rate adaptation layer 16 at an even slower rate of 300 bits per second, RA0 converting function would repeat more data.
Besides buffering data with different transmission speeds, rate adaptation layer 16 also needs to perform format converting on the inputted data, and then transmit the converted data out. Please refer to FIGS. 2A to 2D, which illustrates four different types of data format converting, where data A is to be converted data B, and A0, A1 to A7 represent different bit of data A, with A0 being the Most Significant Bit (MSB). Similarly, B0, B1, etc. represent different bit of data B, with B0 being the most significant bit (MSB). The basic data format converting at rate adaptation layer 16 includes four types, as illustrated in FIGS. 2A to 2D and as follows:
(1) Modify the bit sequence of the un-converted data (data A). For instance, as illustrated in FIG. 2A, B0 of the converted data B is A5 of data A, B1 is A3, and B7 is A4.
(2) Insert additional data or instruction bits into unconverted data (data A). As illustrated in FIG. 2B, two control bits, C0 and C1, are inserted and become B4 and B8 respectively of converted data B.
(3) Erase part of the unconverted data (data A). For instance, as illustrated in FIG. 2C, converted data B corresponds to data A from A1 to A6, with bit A0 and A7 erased.
(4) Insert a logical operation result of unconverted data (data A). As illustrated in FIG. 2D, besides bits from B0 to B7 corresponding to those from A0 to A7, bits in A could undergo logical operation OP, and the result of the logical operation is inserted in B. For instance, OP could be a parity check on data A, and the parity check value is inserted into data B. As illustrated in FIG. 2D, the result of OP becomes bit B8 in data B. Certainly, the result of OP could be inserted to any other location in data B.
With the prior art digital communication system, a micro-controller is used to realize data buffering and format converting functions in the rate adaptation layer. In data buffering, the micro-controller is capable of repeating data with slower transmission rate, or insert instruction or other bits to generate data with higher transmission rate. Assuming the data transmission rate into the rate adaptation layer is not constant (sometimes with higher transmission rate; sometimes with lower), the micro-controller is capable of temporarily storing certain input data, which renders a uniform transmission rate for output data from the rate adaptation layer. In data format converting capability, the micro-controller of the prior art technology performs the converting by executing a program comprising pre-determined sets of instructions. Generally speaking, instruction set residing in the micro-controller combines various functions, the likes of bit shift in the buffer and bit OP, so as to perform the operations it needs for data format converting. For instance, when the micro-controller undergoes data format converting as illustrated in FIG. 2A, converting bits in data A from [A7, A6, A5, A4, A3, A2, A1, A0] to [A4, A0, A7, A1, A6, A2, A3, A5] in data B, the following steps are performed:
Step 1: reset all bits in a destination buffer AR. For example, all bits in the destination buffer AR are reset to zero.
Step 2: copy data A onto another buffer BR.
Step 3: via AND operation on bits, mask out bits from A7 to A1 in BR, which combines [A7, A6, A5, A4, A3, A2, A1, A0] and [0, 0, 0, 0, 0, 0, 0, 1] (a mask data) into [0, 0, 0, 0, 0, 0, 0, A0].
Step 4: via bit shifting, transform [0, 0, 0, 0, 0, 0, 0, A0] into [0, A0, 0, 0, 0, 0, 0, 0].
Step 5: Execute OR operation on bits in both BR and AR, which renders [0, A0, 0, 0, 0, 0, 0, 0] in AR—thus completing the movement on a single bit.
As for other bits in data A, repeat the above steps from 1 to 4 (wherein step 3 uses different mask data, and in step 4 shift bit to different position), thus completing the data format converting in FIG. 2A. Other types of data format converting get accomplished in a similar fashion.
When undertaking data buffer processing and adjusting the data transmission rate, the micro-controller is called upon to handle various logical considerations and operations. However with the prior art technology, the micro-controller is also called upon to handle data format converting in accordance with an instruction set program. Since the micro-controller instruction set program is unable to directly depict data format converting, it calls for a cumbersome process to complete the data format converting. As mentioned earlier, a simple bit shift in the prior art technology requires going from step 1 to step 4. And within each step, there are additional details to go through (for instance, in step 4 micro-controller achieves only 1 bit shift per operation pulse cycle). So to use the prior art method in achieving data format converting would be too time consuming and taking up too many micro-controller resources. As data flow edges upward in todays digital communications, so do stringent requirements on the processing speed. The prior art method of using the instruction set program and the micro-controller for data format converting would definitely be hard pressed to cope with the high requirements for data processing efficiency of contemporary digital signal systems.